A Methodology for Exploring Communication Architectures of Clustered Vliw Processors

VLIW processors have started gaining acceptance in the embedded systems domain. However, monolithic register file VLIW processors with a large number of functional units are not viable. This is because of the need for a large number of ports to support FU requirements, which makes them expensive and extremely slow. A simple solution is to break up this register file into a number of small register files with a subset of FUs connected to it. These architectures are termed as clustered VLIW processors. This thesis focuses on customizing inter-cluster inter-connection networks (ICN) in high issue-rate clustered VLIW processors. While a wide variety of inter-cluster ICNs are reported in literature what is missing is a quantitative evaluation of this design-space. Researchers have used specific tools and methodologies for architecting such VLIW processors, wherein some of the other ICNs are qualitatively eliminated. We build a basis for exploring high issue-rate processor by showing that on an average the media applications [could have an ILP of 20 or even higher]. Towards this end we classify the previous reported results on ILP measurement, coining a novel measurement technique, Achievable-H ILP, which is useful for predicting future architecture requirements. We present a methodology along with the supporting tool chain for exploring the design-space of inter-cluster ICNs. We also classify the previously used architectures and demonstrate that a vast part of this design-space is currently [unexplored]. We conclusively establish that most of the bus-based RF-toRF style ICNs are heavily performance constrained. Finally to prove the superiority of point-to-point type ICNs we develop a parameterized clustered VLIW generator. Using the generated architectures as input to industry standard synthesis, place and route tools we present results on the implementation characterstics of the various ICNs.